Synchronizing phase shift corrected synchronous signal detecting apparatus

ABSTRACT

In a system for eliminating time base fluctuation of a video signal having a synchronizing signal and a burst reproduced from a video disk, for example, the synchronism is first coarsely pulled in on the basis of the horizontal synchronizing signal and then precisely follows the time base fluctuation on the basis of the burst signal. A shift of the output synchronizing signal is corrected by using a phase detection of an input horizontal synchronizing signal when an output synchronizing signal is produced on the basis of the read address of a memory for eliminating time base fluctuation, thereby preventing, for example, a superimposed character using the output synchronizing signal from fluctuating on a picture.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a synchronizing signal detectingapparatus of a reproducing apparatus for a video disk or other recordingmedium.

2. Description of a Prior Art

Conventionally, a digital time base corrector has been practically usedwhich enables a video signal of a corrected time base to be obtainedfrom a reproduced signal of a video disk, for example, having time basefluctuation such as jitter, by writing the reproduced signal in adigital memory in synchronism with the fluctuated time base and readingit with a fixed clock. In such an apparatus, a synchronizing signaldrives a character generator for superimposing characters, for example,with an output signal. The synchronizing signal is separately detectedin analog form from the video signal of the corrected time base. Thereason for this is as follows.

Usually, in a steady state the digital time base corrector detects timebase fluctuation not based on a horizontal synchronizing signal of theinput video signal but instead based only on a burst signal. Therefore,in the case where the signal is recorded on the disk so that a phase ofthe burst signal in the video signal is shifted at a portion where apicture is changed to another picture (e.g., a program is changed toanother program), or in the case where a burst phase detecting circuitfor detecting time base error is locked in a condition shifted byintegral times of 360 degrees of the burst phase, the location of thevideo signal written on the memory for time base correction is changed.Thus, if the character for super-imposition is produced in accordancewith a synchronizing signal generated on the basis of a read address ofthe memory, the location of the character relative to the video signalis changed. Accordingly, it is necessary to detect the synchronizingsignal for generating characters not on the basis of the memory address,but instead on the basis of the analog signal converted from the videosignal after correcting the time base. This causes a problem in that thesize of the circuit becomes large, and it is impossible to process theentire signal digitally.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a synchronizing signaldetecting circuit which does not synchronizing signal detecting analogoperation circuit and which is able to accurately detect thesynchronizing signal in digital form and supply the synchronizing signalto the character generator, for example.

In order to achieve the above-mentioned object, a synchronizing signaldetecting apparatus according to the present invention comprises areproducing means for reproducing a signal recorded on a recordingmedium, a first phase detecting means for detecting a phase of a firstsynchronizing signal detected from a reproduced signal, means foranalog-digital converting the reproduced signal, a second phasedetecting means for detecting a phase of a burst signal of an output ofthe analog-digital converting means, phase synchronous oscillating meanscontrolled by outputs of the first and second phase detecting means,synchronism shift amount detecting means for converting the output ofthe first phase detecting means to a corresponding number of clocks ofan output clock of the phase synchronous oscillating means, digitalmemory means for eliminating a time base error from the output of theanalog-digital converting means, means for generating a read addresssignal for the digital memory means, and synchronizing signal producingmeans for producing a second synchronizing signal using the outputs ofthe address signal generating means and synchronism shift amountdetecting means.

According to the invention, the horizontal synchronizing signal producedon the basis of a read address counter of the memory for time basecorrection is always obtained in coincidence with the output videosignal of the corrected time base.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a first embodiment of the invention;

FIGS. 2 (a-d) are a chart showing timings of signals;

FIG. 3 is a block diagram showing a second embodiment of the invention;

FIG. 4 is a block diagram showing a third embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a first embodiment of the invention.

Referring to this figure, 1 denotes a video disk, and 2 denotes a diskdriving apparatus which comprises a motor and a motor driving circuitand rotates the disk 1. 3 denotes a pickup which reads out a signal fromthe video disk 1, and 4 denotes a FM demodulating circuit whichdemodulates a modulated signal detected by the pickup 3 to an originalvideo signal. 5 denotes an analog-digital converter (A/D) which convertsthe demodulated signal to a digital signal. 6 denotes a memory intowhich the output signal of the A/D 5 is written with a clocksynchronized with the demodulated signal of a fluctuated time base andfrom which the signal is read with another clock of a steady time base,so as to obtain a digital video signal of a corrected time base. 7denotes a digital adding circuit for adding digitally a character signalgenerated as a digital signal. 8 denotes a digital-analog converter(D/A) which demodulates the digital video signal to the original analogsignal. 9 denotes an output terminal of the reproduced video signal. 10denotes a first synchronizing signal detecting circuit which detects ahorizontal synchronizing signal in analog form from the demodulatedvideo signal. 11 denotes a burst detecting circuit which detects a burstdigitally from the digital converted video signal. 12 denotes a firstphase detecting circuit which detects and outputs a phase differencebetween the horizontal synchronizing signal supplied from the firstsynchronizing signal detecting circuit 10 and a horizontal synchronizingpulse produced by frequency dividing a clock signal of an output of alater-described voltage controlled oscillating circuit 15. 13 denotes asecond phase detecting circuit which detects and outputs a phasedifference between the burst signal supplied from the burst detectingcircuit 11 and a burst pulse produced by frequency dividing the clocksignal output from the voltage controlled oscillating circuit 15. 14denotes a selector circuit which switches the outputs of the first andsecond phase detecting circuits 12 and 13 and supplies the selectedoutput to the voltage controlled oscillating circuit 15.

In the above-mentioned construction, the two phase detecting circuits 12and 13 are selectively used so that the synchronism is first coarselypulled in on the basis of the horizontal synchronizing signal andthereafter precisely follows the time base fluctuation on the basis ofthe burst signal.

The voltage controlled oscillating circuit 15 is controlled in itsoscillation frequency and phase by an externally supplied voltage. 16denotes a first dividing circuit which divides the frequency of theoutput clock signal of the voltage controlled oscillating circuit 15 toobtain the horizontal synchronizing pulse and the burst pulse, andsupply them to the first and second phase detecting circuits 12 and 13.17 denotes a write address counter which is driven with the output clockof the voltage controlled oscillating circuit 15 and generates a writeaddress for the memory 6 on the basis of the horizontal synchronizingpulse. 18 denotes a source oscillating circuit which generates a stableclock which is free from time base fluctuation. 19 denotes a readaddress counter which is driven by the clock obtained from the output ofthe source oscillating circuit 18 and supplies a read address for thememory 6. 20 denotes a second dividing circuit which divides the outputclock of the source oscillating circuit 18 to obtain a standardhorizontal synchronizing pulse. 21 denotes a third phase detectingcircuit which compares the phase of the standard horizontalsynchronizing pulse with the phase of the horizontal synchronizingsignal of the output of the first synchronizing signal detecting circuit10 and controls the disk driving apparatus 2 responsive to the thusobtained phase difference signal. 22 denotes a character generator whichgenerates data such as characters, for example to be superimposed withthe video signal by the adding circuit 7.

23 denotes a phase shift amount detecting circuit which converts thephase shift detecting output of the first phase detecting circuit 12 toa corresponding number of clocks and outputs it. An actual embodimentthereof is explained hereinafter, referring to FIG. 2. In FIG. 2,waveform a shows the reproduced video signal of the fluctuated timebase, and 30 denotes a digital sampling point. Waveforms b and c showthe horizontal synchronizing pulse and the burst pulse, respectively,produced by the first dividing circuit 16. Waveform d shows the clocksignal supplied from the voltage controlled oscillating circuit 15. Inthe case where the frequency of the clock signal is set four times aslarge as that of the burst frequency, the burst pulse c has a period offour clock periods as shown in the figure. Therefore, in the steadystate, i.e. the state in which the switch 14 is connected to the side ofthe output terminal of the second phase detecting circuit 13, since timebase correction is operated only on the basis of the burst, pulse ashift which is integral times the burst period, i.e. 4-clock unit,cannot be detected. On the other hand, since the first phase detectingcircuit 12 outputs the detected signal denoting the phase differencebetween the horizontal synchronizing signal and the horizontalsynchronizing pulse, it is possible to convert this phase difference toa value k (k represents a positive or negative integer) by thesynchronism shift amount detecting circuit 12 as shown in FIG. 2. Inconnection with FIG. 2, in the case where the time base correction isoperated only in response to the burst phase, if a phase shift of theburst signal occurs in relation to the synchronizing signal of thereproduced video signal, the phase of the synchronizing pulse is alsoshifted. However, no problem is presented, because the shift amount isdetected.

Referring again to FIG. 1, 24 denotes a decoding circuit which decodes aparticular address number from the output of the read address counter 19and outputs it as a horizontal synchronizing signal for the charactergenerator 22. A vertical synchronizing signal for character is producedby another circuit which is not shown in the figure. For example, ifnormally the address j (j represents an integer) is to be decoded as thesynchronizing signal, correspondingly to the output k of the synchronismshift amount detecting circuit 23 address (j-k) is produced as thesynchronizing signal. Thus, even if the location of the synchronizingsignal of the video signal read from the memory is shifted from that ofthe read address, the synchronizing signal for the character generator22 is always located at the same position as that of the synchronizingsignal of the video signal.

The reason for once converting to a value of 1 clock unit by thesynchronism shift amount detecting circuit 23 is that the detected phasedifference amount cannot be used directly in the reading side, becauseof a time base shift between the writing side and the reading side ofthe memory 6 due to the effect of time base correction.

A second embodiment is explained hereinafter, referring to FIG. 3. Inthis figure, 44 denotes a base-n counter (n represents a positiveinteger) which counts the clock supplied from the source oscillatingcircuit 18. This base-n counter starts counting at the moment when theaddress of the read address counter 19 becomes a particular value, i.e.number j, or starts counting by a starting signal which is a repeatedsignal having the same period as that of the read address such as acounter reset pulse or load pulse of the address counter obtained fromthe read address counter 19, and counts until an n count, to output thehorizontal synchronizing signal for the character generator 22 and thenstops until the next start signal arrives. A vertical synchronizingsignal for the character generator 22 is produced by another circuitwhich is not shown. At that time the counter value is made (n-k) by theuse of the output value k of the synchronism shift amount detectingcircuit 23. According to this construction, the size of the circuit isreduced compared with the first embodiment in which it is necessary tovary the decode value.

A third embodiment is described hereinafter, referring ring to FIG. 4.45 denotes a timing pulse generating circuit which generates a resettiming pulse. The construction thereof is the same as that of thebase-(n-k) counter described in the second embodiment. 46 denotes athird dividing circuit which produces the horizontal and verticalsynchronizing signals from the output clock of the source oscillatingcircuit 18. It is composed of base-h and base-v (h and v are positiveintegers) self-start counters. The values of h and v are constant andset so as to enable the horizontal and vertical synchronizing signals tobe obtained. The synchronizing signal obtained from the third dividingcircuit 46 is supplied to the character generating circuit 23.

This third embodiment has a composition of varying the reset position ofthe third dividing circuit which is used for producing the horizontaland vertical synchronizing signals, in contrast to the first and secondembodiments which only produce the horizontal synchronizing signal forthe character generator 22.

Although the above-mentioned embodiments are described as an apparatusfor generating synchronizing signal for a character generator, theinvention can be also used for producing a synchronizing signal forcontrolling a memory used to operate another signal processing, circuitfor example, special effect reproduction such as still or slow, motionwhich is carried out to the video signal after the time base correctionis made.

Further although the above-mentioned description has been made referringto the video disk, this invention can be applied for a time basecorrector of all other recording and reproducing apparatus.

What is claimed is:
 1. A synchronizing signal detecting apparatuscomprising:reproducing means for reproducing from a recording medium avideo signal recorded on the recording medium to obtain a reproducedvideo signal; synchronizing signal detecting means for detecting fromthe reproduced video signal a synchronizing signal of the reproducedvideo signal; first phase detecting means for detecting a phasedifference between the synchronizing signal and a first phase referencesignal and outputting a first phase difference signal indicative of thedetected phase difference; analog-digital converting means forconverting the reproduced video signal to a digital video signal; burstsignal detecting means for digitally detecting from the digital videosignal a burst signal of the reproduced video signal; second phasedetecting means for detecting a phase difference between the burstsignal and a second phase reference signal and outputting a second phasedifference signal indicative of the detected phase difference; phasesynchronous oscillating means selectively controlled by the first andsecond phase difference signals for generating a first clock signal;frequency dividing means for dividing a frequency of the first clocksignal to obtain the first phase reference signal when said phasesynchronous oscillating means is controlled by the first phasedifference signal and to obtain the second phase reference signal whensaid phase synchronous oscillating means is controlled by the secondphase difference signal; synchronism shift amount detecting means forconverting the phase difference detected by said first phase detectingmeans to a corresponding number of clocks of the first clock signal;write address generating means responsive to the first clock signal forgenerating a write address signal; fixed clock generating means forgenerating a second clock signal which has a fixed phase; read addressgenerating means responsive to the second clock signal for generating aread address signal; digital memory means responsive to the writeaddress signal for writing thereinto the digital video signal andresponsive to the read address signal for reading therefrom the writtendigital video signal to thereby eliminate a time base error from thedigital video signal; and, synchronizing signal producing means forproducing a corrected synchronizing signal which is corrected ofsynchronism shift from an output of said read address generating meansand an output of said synchronism shift amount detecting means.
 2. Asynchronizing signal detecting apparatus as claimed in claim 1, whereinsaid synchronizing signal producing means comprises decoding means fordecoding the output of said read address generating means to apredetermined decode value, said decoding means correcting thepredetermined decode value according to the output of said synchronismshift amount detecting means.
 3. A synchronizing signal detectingapparatus as claimed in claim 1, wherein said synchronizing signalproducing means comprises a counter responsive to the output of saidread address generating means, for starting a counting of clocks of thesecond clock signal until a resultant count value becomes apredetermined count value, said counter varying the predetermined countvalue according to the output of said synchronism shift amount detectingmeans.
 4. A synchronizing signal detecting apparatus as claimed in claim1, wherein said synchronizing signal producing means comprises afrequency dividing circuit for frequency-dividing the second clocksignal to obtain the corrected synchronizing signal, and reset signalgenerating means for generating from the output of said read addressgenerating means a reset signal for resetting the frequency dividingcircuit, said reset signal generating means varying a reset timing ofthe reset signal according to the output of said synchronism shiftamount detecting means.